dorsal/arxiv
View SchemaArchitecture of a Quantum Multicomputer Optimized for Shor's Factoring Algorithm
| Authors | Rodney Doyle Van Meter III |
|---|---|
| Categories | |
| ArXiv ID | quant-ph/0607065 |
| URL | https://arxiv.org/abs/quant-ph/0607065 |
Abstract
The quantum multicomputer consists of a large number of small nodes and a qubus interconnect for creating entangled state between the nodes. The primary metric chosen is the performance of such a system on Shor's algorithm for factoring large numbers: specifically, the quantum modular exponentiation step that is the computational bottleneck. This dissertation introduces a number of optimizations for the modular exponentiation. My algorithms reduce the latency, or circuit depth, to complete the modular exponentiation of an n-bit number from O(n^3) to O(n log^2 n) or O(n^2 log n), depending on architecture. Calculations show that these algorithms are one million times and thirteen thousand times faster, when factoring a 6,000-bit number, depending on architecture. Extending to the quantum multicomputer, five different qubus interconnect topologies are considered, and two forms of carry-ripple adder are found to be the fastest for a wide range of performance parameters. The links in the quantum multicomputer are serial; parallel links would provide only very modest improvements in system reliability and performance. Two levels of the Steane [[23,1,7]] error correction code will adequately protect our data for factoring a 1,024-bit number even when the qubit teleportation failure rate is one percent.
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"abstract": "The quantum multicomputer consists of a large number of small nodes and a\nqubus interconnect for creating entangled state between the nodes. The primary\nmetric chosen is the performance of such a system on Shor\u0027s algorithm for\nfactoring large numbers: specifically, the quantum modular exponentiation step\nthat is the computational bottleneck. This dissertation introduces a number of\noptimizations for the modular exponentiation. My algorithms reduce the latency,\nor circuit depth, to complete the modular exponentiation of an n-bit number\nfrom O(n^3) to O(n log^2 n) or O(n^2 log n), depending on architecture.\nCalculations show that these algorithms are one million times and thirteen\nthousand times faster, when factoring a 6,000-bit number, depending on\narchitecture. Extending to the quantum multicomputer, five different qubus\ninterconnect topologies are considered, and two forms of carry-ripple adder are\nfound to be the fastest for a wide range of performance parameters. The links\nin the quantum multicomputer are serial; parallel links would provide only very\nmodest improvements in system reliability and performance. Two levels of the\nSteane [[23,1,7]] error correction code will adequately protect our data for\nfactoring a 1,024-bit number even when the qubit teleportation failure rate is\none percent.",
"arxiv_id": "quant-ph/0607065",
"authors": [
"Rodney Doyle Van Meter III"
],
"categories": [
"quant-ph"
],
"title": "Architecture of a Quantum Multicomputer Optimized for Shor\u0027s Factoring Algorithm",
"url": "https://arxiv.org/abs/quant-ph/0607065"
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