dorsal/arxiv
View SchemaSingle-Chip 1.024 Tb/s Optical Receiver for High-Speed Optical links
| Authors | Ali Pirmoradi, Zhehao Yu, Amirreza Shoobi, Geun Ho Ahn, Jelena Vučković, Firooz Aflatouni |
|---|---|
| Categories | |
| ArXiv ID | 2601.07709vv1 |
| URL | https://arxiv.org/abs/2601.07709 |
| License | http://creativecommons.org/licenses/by-nc-nd/4.0/ |
Abstract
Integrated optical transceivers, utilizing wavelength-division-multiplexing, offer a path forward for implementation of compact, high-bandwidth and energy-efficient interconnects for future data centers. Here we report the demonstration of a monolithically integrated optical receiver in 45nm CMOS, where efficient multi-layer optical demultiplexing with capacitive tuning, energy efficient electronics and wideband inverse designed grating couplers enable implementation of a 32-channel receiver chip based on wavelength-division multiplexing. The chip operates at an aggregate data-rate of 1.024 Tb/s with all channels operating simultaneously at a data-rate of 32 Gb/s/channel achieving a record energy efficiency of 71 fJ/b, including the power consumption of both the electronic circuitry and the tuning and control of photonic devices, and a record bandwidth density of 4 Tb/s/mm2. The receiver achieves a bit-error-rate below 1E-12 without requiring equalization, error correction or digital processing. Inverse-designed broadband grating couplers provide efficient, low-loss optical coupling into the chip. An on-chip demultiplexer, composed of Mach-Zehnder interferometers (MZIs) and ring resonators, offers a large channel-to-channel isolation sufficient for error-free operation. Capacitive phase shifters embedded within the ring resonators of the demultiplexer are used for wavelength alignment at a zero static power consumption. MZIs and ring-resonators are periodically selected and autonomously locked to the wavelength of the corresponding optical carrier. The implemented monolithic receiver offers a scalable, energy-efficient and reliable solution for the beyond Tb/s optical interconnects.
{
"annotation_id": "c12d4035-791f-4ad6-b67c-75409a803dc7",
"date_created": "2026-02-17T05:53:12.529000Z",
"date_modified": "2026-02-17T05:53:12.529000Z",
"file_hash": "dd16e6e167b67fe2cc39487775d1b27e6c448c94dff7b1eaada3cf8067326c3c",
"private": false,
"record": {
"abstract": "Integrated optical transceivers, utilizing wavelength-division-multiplexing, offer a path forward for implementation of compact, high-bandwidth and energy-efficient interconnects for future data centers. Here we report the demonstration of a monolithically integrated optical receiver in 45nm CMOS, where efficient multi-layer optical demultiplexing with capacitive tuning, energy efficient electronics and wideband inverse designed grating couplers enable implementation of a 32-channel receiver chip based on wavelength-division multiplexing. The chip operates at an aggregate data-rate of 1.024 Tb/s with all channels operating simultaneously at a data-rate of 32 Gb/s/channel achieving a record energy efficiency of 71 fJ/b, including the power consumption of both the electronic circuitry and the tuning and control of photonic devices, and a record bandwidth density of 4 Tb/s/mm2. The receiver achieves a bit-error-rate below 1E-12 without requiring equalization, error correction or digital processing. Inverse-designed broadband grating couplers provide efficient, low-loss optical coupling into the chip. An on-chip demultiplexer, composed of Mach-Zehnder interferometers (MZIs) and ring resonators, offers a large channel-to-channel isolation sufficient for error-free operation. Capacitive phase shifters embedded within the ring resonators of the demultiplexer are used for wavelength alignment at a zero static power consumption. MZIs and ring-resonators are periodically selected and autonomously locked to the wavelength of the corresponding optical carrier. The implemented monolithic receiver offers a scalable, energy-efficient and reliable solution for the beyond Tb/s optical interconnects.",
"arxiv_id": "2601.07709",
"authors": [
"Ali Pirmoradi",
"Zhehao Yu",
"Amirreza Shoobi",
"Geun Ho Ahn",
"Jelena Vu\u010dkovi\u0107",
"Firooz Aflatouni"
],
"categories": [
"physics.optics",
"physics.app-ph"
],
"license": "http://creativecommons.org/licenses/by-nc-nd/4.0/",
"title": "Single-Chip 1.024 Tb/s Optical Receiver for High-Speed Optical links",
"url": "https://arxiv.org/abs/2601.07709",
"version": "v1"
},
"schema_id": "dorsal/arxiv",
"source": {
"execution_id": "80524fbe-90c4-43c9-a713-d0e47dd174fd",
"id": "arXiv Dataset",
"type": "Model",
"variant": "snapshot-2026-01-17",
"version": "0.1.0"
},
"user_id": 1000002
}