dorsal/arxiv
View SchemaEnhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization
| Authors | Binglei Lou, Ruilin Wu, Philip Leong |
|---|---|
| Categories | |
| ArXiv ID | 2601.09773vv1 |
| URL | https://arxiv.org/abs/2601.09773 |
| DOI | 10.1109/TCAD.2026.3654908 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems (TCAD), 2025 |
| License | http://arxiv.org/licenses/nonexclusive-distrib/1.0/ |
Abstract
Deploying deep neural networks (DNNs) on resource-constrained edge devices such as FPGAs requires a careful balance among latency, power, and hardware resource usage, while maintaining high accuracy. Existing Lookup Table (LUT)-based DNNs -- such as LogicNets, PolyLUT, and NeuraLUT -- face two critical challenges: the exponential growth of LUT size and inefficient random sparse connectivity. This paper presents SparseLUT, a comprehensive framework that addresses these challenges through two orthogonal optimizations. First, we propose an architectural enhancement that aggregates multiple PolyLUT sub-neurons via an adder, significantly reducing LUT consumption by 2.0x-13.9x and lowering inference latency by 1.2x-1.6x, all while maintaining comparable accuracy. Building upon this foundation, we further introduce a non-greedy training algorithm that optimizes neuron connectivity by selectively pruning less significant inputs and strategically regrowing more effective ones. This training optimization, which incurs no additional area and latency overhead, delivers consistent accuracy improvements across benchmarks -- achieving up to a 2.13% gain on MNIST and 0.94% on Jet Substructure Classification compared to existing LUT-DNN approaches.
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"abstract": "Deploying deep neural networks (DNNs) on resource-constrained edge devices such as FPGAs requires a careful balance among latency, power, and hardware resource usage, while maintaining high accuracy. Existing Lookup Table (LUT)-based DNNs -- such as LogicNets, PolyLUT, and NeuraLUT -- face two critical challenges: the exponential growth of LUT size and inefficient random sparse connectivity. This paper presents SparseLUT, a comprehensive framework that addresses these challenges through two orthogonal optimizations. First, we propose an architectural enhancement that aggregates multiple PolyLUT sub-neurons via an adder, significantly reducing LUT consumption by 2.0x-13.9x and lowering inference latency by 1.2x-1.6x, all while maintaining comparable accuracy. Building upon this foundation, we further introduce a non-greedy training algorithm that optimizes neuron connectivity by selectively pruning less significant inputs and strategically regrowing more effective ones. This training optimization, which incurs no additional area and latency overhead, delivers consistent accuracy improvements across benchmarks -- achieving up to a 2.13% gain on MNIST and 0.94% on Jet Substructure Classification compared to existing LUT-DNN approaches.",
"arxiv_id": "2601.09773",
"authors": [
"Binglei Lou",
"Ruilin Wu",
"Philip Leong"
],
"categories": [
"cs.AR",
"cs.AI"
],
"doi": "10.1109/TCAD.2026.3654908",
"journal_ref": "IEEE Transactions on Computer-Aided Design of Integrated Circuits \u0026 Systems (TCAD), 2025",
"license": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
"title": "Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization",
"url": "https://arxiv.org/abs/2601.09773",
"version": "v1"
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