{
  "annotation_id": "7d539612-fbe0-4fd6-b12a-73955a2f3239",
  "date_created": "2026-03-02T18:00:46.915000Z",
  "date_modified": "2026-03-02T18:00:46.915000Z",
  "file_hash": "e773673a230daad767a2541eb58243886fafb4dc899569530fde4e37aa33e896",
  "private": false,
  "record": {
    "abstract": "A pipeline CAMAC controller with PC/104-Plus single board computer has been\ndeveloped. The architecture of the pipeline CAMAC controller is completely\ndifferent from that of traditional CAMAC controller. The pipeline CAMAC\ncontroller adopted truly pipelined command and data paths from/to computer\nmemory to/from CAMAC. The pipeline method enabled the controller maximum speed\nof CAMAC, approximately up to 3 MB/sec with 24-bit data. The controller also\nhas a DAQ function such as event numbering for co-existence with other\nequipment such as VME. Not only the functionality and the performance but also\nthe pipeline architecture and the design concept are described.",
    "arxiv_id": "physics/0307071",
    "authors": [
      "Y. Yasu",
      "E. Inoue",
      "H. Fujii",
      "Y. Igarashi",
      "M. Ikeno",
      "M. Tanaka",
      "K. Nakayoshi",
      "H. Kodama",
      "S. Harada",
      "H. Kyoo"
    ],
    "categories": [
      "physics.ins-det"
    ],
    "title": "Development of a pipeline CAMAC controller with PC/104-Plus single board   computer",
    "url": "https://arxiv.org/abs/physics/0307071"
  },
  "schema_id": "dorsal/arxiv",
  "source": {
    "execution_id": "5af4295f-6efc-4e3c-89ed-a4a44037e813",
    "id": "arXiv Dataset IDs",
    "type": "Model",
    "variant": "snapshot-2026-03-01",
    "version": "0.1.0"
  },
  "user_id": 1000002
}