{
  "annotation_id": "789058dd-d7ca-4449-9ce9-7071aebc2215",
  "date_created": "2026-03-02T18:02:31.149000Z",
  "date_modified": "2026-03-02T18:02:31.149000Z",
  "file_hash": "20b3bc8b96f616cef7d71007fa88e77d0d739174ab416b02596e3858d6fe3b2e",
  "private": false,
  "record": {
    "abstract": "Quantum error correction and fault-tolerant quantum computation are two\nfundamental concepts which make quantum computing feasible. While providing a\ntheoretical means with which to ensure the arbitrary accuracy of any quantum\ncircuit, fault-tolerant error correction is predicated upon the robust\npreparation of logical states. An optimal direct circuit and a more complex\nfault-tolerant circuit for the preparation of the [[7,1,3]] Steane logical-zero\nare simulated in the presence of discrete quantum errors to quantify the regime\nwithin which fault-tolerant preparation of logical states is preferred.",
    "arxiv_id": "quant-ph/0608112",
    "authors": [
      "A. M. Stephens",
      "S. J. Devitt",
      "A. G. Fowler",
      "J. C. Ang",
      "L. C. L. Hollenberg"
    ],
    "categories": [
      "quant-ph"
    ],
    "title": "Gate-level simulation of logical state preparation",
    "url": "https://arxiv.org/abs/quant-ph/0608112"
  },
  "schema_id": "dorsal/arxiv",
  "source": {
    "execution_id": "b1751450-510b-4ecd-b7b3-5aeacd1d3d36",
    "id": "arXiv Dataset IDs",
    "type": "Model",
    "variant": "snapshot-2026-03-01",
    "version": "0.1.0"
  },
  "user_id": 1000002
}