dorsal/arxiv
View SchemaFront End CAMAC Controller for SLAC Control System
| Authors | M. J. Browne, A. E. Gromme, E. J. Siskind |
|---|---|
| Categories | |
| ArXiv ID | physics/0111032 |
| URL | https://arxiv.org/abs/physics/0111032 |
| Journal | eConf C011127 (2001) WEAP022 |
Abstract
Most of the devices in the SLAC control system are accessed via interface modules in ~450 CAMAC crates. Low-cost controllers in these crates communicate via a SLAC-proprietary bit-serial protocol with 77 satellite control computers ("micros") within the accelerator complex. A proposed upgrade replaces the existing Multibus-I implementation of the micro hardware with commercial-off-the-shelf ("COTS") personal computers. For increased reliability and ease of maintenance, these micros will move from their current electrically noisy and environmentally challenging sites to the control center's computer room, with only a stand-alone portion of each micro's CAMAC interface remaining in the micro's original location. This paper describes the hardware/software architecture of that intelligent front-end CAMAC controller and the accompanying fiber optic link board that connects it to the PC-based micro's PCI bus. Emphasis is placed on the hardware/software techniques employed to minimize real-time latency for pulse-to-pulse operations that control accelerator timing, acquire data for fast feedback loops, and change device settings to close those loops. The controller provides the sole interface between the COTS computing/networking environment and the existing CAMAC plant. It also supports higher bandwidth commercial byte-serial crate controllers and legacy BITBUS hardware.
{
"annotation_id": "73652cd3-4142-4333-b1ca-dc6c97c01ebf",
"date_created": "2026-03-02T18:00:35.449000Z",
"date_modified": "2026-03-02T18:00:35.449000Z",
"file_hash": "aadbb47b0ef48466312799d321d09683dc8f4e32ca27de5a23043135606e44b5",
"private": false,
"record": {
"abstract": "Most of the devices in the SLAC control system are accessed via interface\nmodules in ~450 CAMAC crates. Low-cost controllers in these crates communicate\nvia a SLAC-proprietary bit-serial protocol with 77 satellite control computers\n(\"micros\") within the accelerator complex. A proposed upgrade replaces the\nexisting Multibus-I implementation of the micro hardware with\ncommercial-off-the-shelf (\"COTS\") personal computers. For increased reliability\nand ease of maintenance, these micros will move from their current electrically\nnoisy and environmentally challenging sites to the control center\u0027s computer\nroom, with only a stand-alone portion of each micro\u0027s CAMAC interface remaining\nin the micro\u0027s original location. This paper describes the hardware/software\narchitecture of that intelligent front-end CAMAC controller and the\naccompanying fiber optic link board that connects it to the PC-based micro\u0027s\nPCI bus. Emphasis is placed on the hardware/software techniques employed to\nminimize real-time latency for pulse-to-pulse operations that control\naccelerator timing, acquire data for fast feedback loops, and change device\nsettings to close those loops. The controller provides the sole interface\nbetween the COTS computing/networking environment and the existing CAMAC plant.\nIt also supports higher bandwidth commercial byte-serial crate controllers and\nlegacy BITBUS hardware.",
"arxiv_id": "physics/0111032",
"authors": [
"M. J. Browne",
"A. E. Gromme",
"E. J. Siskind"
],
"categories": [
"physics.ins-det"
],
"journal_ref": "eConf C011127 (2001) WEAP022",
"title": "Front End CAMAC Controller for SLAC Control System",
"url": "https://arxiv.org/abs/physics/0111032"
},
"schema_id": "dorsal/arxiv",
"source": {
"execution_id": "99c6767f-8de1-49c4-92ca-8d7f93ce0723",
"id": "arXiv Dataset IDs",
"type": "Model",
"variant": "snapshot-2026-03-01",
"version": "0.1.0"
},
"user_id": 1000002
}