{
  "annotation_id": "6e179e28-1425-4a8a-b60e-8a0afa050a6a",
  "date_created": "2026-02-17T05:53:15.438000Z",
  "date_modified": "2026-02-17T05:53:15.438000Z",
  "file_hash": "3a589ca9cdaa11c8d747934d2487c40ecb5dce62c1440bf4e058317c5770d983",
  "private": false,
  "record": {
    "abstract": "Particle-in-Cell (PIC) simulations spend most of their execution time on particle--grid interactions, where fine-grained atomic updates become a major bottleneck on traditional many-core CPUs. Recent CPU architectures integrate specialized Matrix Processing Units (MPUs) that efficiently support matrix outer-product operations, offering new opportunities to overcome this limitation. Leveraging this architectural shift, this work focuses on redesigning the current deposition step of PIC simulations under a matrix-centric execution model.\n  We present MatrixPIC, the first holistic co-design of the deposition kernel, data layout, and incremental particle sorting tailored to the hybrid MPU--VPU SIMD model on modern CPUs. MatrixPIC introduces: (i)~a block-matrix formulation of the current deposition algorithm that maps naturally to MPU outer-product primitives; (ii)~a hybrid execution pipeline that combines MPU-based high-density accumulation with VPU-based data preparation and control flow; and (iii)~an $O(1)$-amortized incremental sorter based on a gapped packed-memory array to preserve data locality for efficient MPU execution.\n  Evaluated on a next-generation HPC platform, MatrixPIC achieves significant performance gains. In Laser-Wakefield Acceleration (LWFA) simulations, it delivers up to $2.63\\times$ speedup in total runtime. For third-order deposition, the core kernel is accelerated by $8.7\\times$ over the baseline and $2.0\\times$ over the best hand-optimized VPU implementation. Moreover, MatrixPIC reaches $83.08\\%$ of theoretical CPU peak performance, nearly $2.8\\times$ higher than a highly optimized CUDA kernel on a data center GPU. These results demonstrate the effectiveness of matrix-oriented co-design for accelerating PIC simulations on emerging CPU architectures.",
    "arxiv_id": "2601.08277",
    "authors": [
      "Yizhuo Rao",
      "Xingjian Cui",
      "Jiabin Xie",
      "Shangzhi Pang",
      "Guangnan Feng",
      "Jinhui Wei",
      "Zhiguang Chen",
      "Yutong Lu"
    ],
    "categories": [
      "cs.DC"
    ],
    "doi": "10.1145/3767295.3769378",
    "license": "http://creativecommons.org/licenses/by/4.0/",
    "title": "Matrix-PIC: Harnessing Matrix Outer-product for High-Performance Particle-in-Cell Simulations",
    "url": "https://arxiv.org/abs/2601.08277",
    "version": "v1"
  },
  "schema_id": "dorsal/arxiv",
  "source": {
    "execution_id": "c87dabcf-1dc4-45b9-ad19-b0a04a923986",
    "id": "arXiv Dataset",
    "type": "Model",
    "variant": "snapshot-2026-01-17",
    "version": "0.1.0"
  },
  "user_id": 1000002
}