dorsal/arxiv
View SchemaResistive Memory based Efficient Machine Unlearning and Continual Learning
| Authors | Ning Lin, Jichang Yang, Yangu He, Zijian Ye, Kwun Hang Wong, Xinyuan Zhang, Songqi Wang, Yi Li, Kemi Xu, Leo Yu Zhang, Xiaoming Chen, Dashan Shang, Han Wang, Xiaojuan Qi, Zhongrui Wang |
|---|---|
| Categories | |
| ArXiv ID | 2601.10037vv1 |
| URL | https://arxiv.org/abs/2601.10037 |
| License | http://arxiv.org/licenses/nonexclusive-distrib/1.0/ |
Abstract
Resistive memory (RM) based neuromorphic systems can emulate synaptic plasticity and thus support continual learning, but they generally lack biologically inspired mechanisms for active forgetting, which are critical for meeting modern data privacy requirements. Algorithmic forgetting, or machine unlearning, seeks to remove the influence of specific data from trained models to prevent memorization of sensitive information and the generation of harmful content, yet existing exact and approximate unlearning schemes incur prohibitive programming overheads on RM hardware owing to device variability and iterative write-verify cycles. Analogue implementations of continual learning face similar barriers. Here we present a hardware-software co-design that enables an efficient training, deployment and inference pipeline for machine unlearning and continual learning on RM accelerators. At the software level, we introduce a low-rank adaptation (LoRA) framework that confines updates to compact parameter branches, substantially reducing the number of trainable parameters and therefore the training cost. At the hardware level, we develop a hybrid analogue-digital compute-in-memory system in which well-trained weights are stored in analogue RM arrays, whereas dynamic LoRA updates are implemented in a digital computing unit with SRAM buffer. This hybrid architecture avoids costly reprogramming of analogue weights and maintains high energy efficiency during inference. Fabricated in a 180 nm CMOS process, the prototype achieves up to a 147.76-fold reduction in training cost, a 387.95-fold reduction in deployment overhead and a 48.44-fold reduction in inference energy across privacy-sensitive tasks including face recognition, speaker authentication and stylized image generation, paving the way for secure and efficient neuromorphic intelligence at the edge.
{
"annotation_id": "56cb491d-5f30-4934-bec0-9433704010cf",
"date_created": "2026-02-17T05:53:24.091000Z",
"date_modified": "2026-02-17T05:53:24.091000Z",
"file_hash": "9fb8b3218a6d671bfe8c60fe89043b9b1f8b1a0c07bfe7111fbb0cd132dc8f4a",
"private": false,
"record": {
"abstract": "Resistive memory (RM) based neuromorphic systems can emulate synaptic plasticity and thus support continual learning, but they generally lack biologically inspired mechanisms for active forgetting, which are critical for meeting modern data privacy requirements. Algorithmic forgetting, or machine unlearning, seeks to remove the influence of specific data from trained models to prevent memorization of sensitive information and the generation of harmful content, yet existing exact and approximate unlearning schemes incur prohibitive programming overheads on RM hardware owing to device variability and iterative write-verify cycles. Analogue implementations of continual learning face similar barriers. Here we present a hardware-software co-design that enables an efficient training, deployment and inference pipeline for machine unlearning and continual learning on RM accelerators. At the software level, we introduce a low-rank adaptation (LoRA) framework that confines updates to compact parameter branches, substantially reducing the number of trainable parameters and therefore the training cost. At the hardware level, we develop a hybrid analogue-digital compute-in-memory system in which well-trained weights are stored in analogue RM arrays, whereas dynamic LoRA updates are implemented in a digital computing unit with SRAM buffer. This hybrid architecture avoids costly reprogramming of analogue weights and maintains high energy efficiency during inference. Fabricated in a 180 nm CMOS process, the prototype achieves up to a 147.76-fold reduction in training cost, a 387.95-fold reduction in deployment overhead and a 48.44-fold reduction in inference energy across privacy-sensitive tasks including face recognition, speaker authentication and stylized image generation, paving the way for secure and efficient neuromorphic intelligence at the edge.",
"arxiv_id": "2601.10037",
"authors": [
"Ning Lin",
"Jichang Yang",
"Yangu He",
"Zijian Ye",
"Kwun Hang Wong",
"Xinyuan Zhang",
"Songqi Wang",
"Yi Li",
"Kemi Xu",
"Leo Yu Zhang",
"Xiaoming Chen",
"Dashan Shang",
"Han Wang",
"Xiaojuan Qi",
"Zhongrui Wang"
],
"categories": [
"cs.ET"
],
"license": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
"title": "Resistive Memory based Efficient Machine Unlearning and Continual Learning",
"url": "https://arxiv.org/abs/2601.10037",
"version": "v1"
},
"schema_id": "dorsal/arxiv",
"source": {
"execution_id": "866fdad0-fd6b-48bd-af24-1c47d53d0010",
"id": "arXiv Dataset",
"type": "Model",
"variant": "snapshot-2026-01-17",
"version": "0.1.0"
},
"user_id": 1000002
}