dorsal/arxiv
View SchemaThe CDF Silicon Vertex Trigger
| Authors | CDF Collaboration |
|---|---|
| Categories | |
| ArXiv ID | physics/0306169 |
| URL | https://arxiv.org/abs/physics/0306169 |
| DOI | 10.1016/j.nima.2003.11.078 |
| Journal | Nucl.Instrum.Meth.A518:532-536,2004 |
Abstract
The CDF experiment's Silicon Vertex Trigger is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 microsecond pipeline. SVT's 35 micron impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common inter-board data link, and a universal "Merger" board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.
{
"annotation_id": "0fdb326f-69d2-4508-bf55-94d089babe06",
"date_created": "2026-03-02T18:00:46.673000Z",
"date_modified": "2026-03-02T18:00:46.673000Z",
"file_hash": "8e1f430dd434b67a96d1b64334017ec66dfad2461e295cbd07f38d19733be8dc",
"private": false,
"record": {
"abstract": "The CDF experiment\u0027s Silicon Vertex Trigger is a system of 150 custom 9U VME\nboards that reconstructs axial tracks in the CDF silicon strip detector in a 15\nmicrosecond pipeline. SVT\u0027s 35 micron impact parameter resolution enables CDF\u0027s\nLevel 2 trigger to distinguish primary and secondary particles, and hence to\ncollect large samples of hadronic bottom and charm decays. We review some of\nSVT\u0027s key design features. Speed is achieved with custom VLSI pattern\nrecognition, linearized track fitting, pipelining, and parallel processing.\nTesting and reliability are aided by built-in logic state analysis and\ntest-data sourcing at each board\u0027s input and output, a common inter-board data\nlink, and a universal \"Merger\" board for data fan-in/fan-out. Speed and\nadaptability are enhanced by use of modern FPGAs.",
"arxiv_id": "physics/0306169",
"authors": [
"CDF Collaboration"
],
"categories": [
"physics.ins-det"
],
"doi": "10.1016/j.nima.2003.11.078",
"journal_ref": "Nucl.Instrum.Meth.A518:532-536,2004",
"title": "The CDF Silicon Vertex Trigger",
"url": "https://arxiv.org/abs/physics/0306169"
},
"schema_id": "dorsal/arxiv",
"source": {
"execution_id": "4cd739dc-51f1-4dce-a456-4117904ae0c6",
"id": "arXiv Dataset IDs",
"type": "Model",
"variant": "snapshot-2026-03-01",
"version": "0.1.0"
},
"user_id": 1000002
}